Title:
クロック位相生成のための方法および装置
Document Type and Number:
Japanese Patent JP7077298
Kind Code:
B2
Abstract:
A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.
Inventors:
Namgun, Jinyun
Raji, Mayank
Upadiyaya, Parag
Mansena, Vinci
Hahn, Catherine
Ellet, Mark
Raji, Mayank
Upadiyaya, Parag
Mansena, Vinci
Hahn, Catherine
Ellet, Mark
Application Number:
JP2019500595A
Publication Date:
May 30, 2022
Filing Date:
May 31, 2017
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
H03L7/083; H03L7/081; H03L7/24
Domestic Patent References:
| JP2010206311A |
Foreign References:
| WO2015073189A1 | ||||
| US6998888 | ||||
| US20140241442 | ||||
| US6259293 |
Attorney, Agent or Firm:
Sonoda/Kobayashi Patent Business Corporation