To read a correct instruction out of an external ROM in returning from a static mode to a normal operation mode when the external ROM is powered off in the static mode.
A microcomputer is provided with a register 3a which previously holds an instruction in a start address of the external ROM that a CPU reads in shifting from the stationary mode to the normal operation mode, a coincidence circuit 4 which decides whether the instruction reads the start address of the external ROM in shifting from the static mode to the normal operation mode matches the instruction held in the register 3a, and a selecting circuit 5 which supplies the instruction read out of the external ROM to the CPU to perform it when the coincidence circuit detects the coincidence between the instruction read out of the start address of the external ROM and the instruction held in the register 3a.
YONAMINE YASUSHI
Hironori Honda
Toshimitsu Ichikawa
Takeshi Takamatsu
Yuriko Kuriu
Next Patent: SYSTEM AND METHOD FOR SUPPORTING INSURANCE AGENT