PURPOSE: To realize a direct connection between an active device and a passive device without sacrificing the address space of a memory, by multiplexing the signal to be used for selection of a module through a bus line.

CONSTITUTION: An active device 1 puts a chip selection signal CS on an address data line AD, turns on a control strobe signal CTS and informs this to a passive device 2. Then the device 1 produces a load address strobe signal RAS and adds a column address to produce a column address strobe signal CAS when necessary. If this access is carried out in the reading cycle, the read data is obtained from the device 2 after having a delay of the access time to the signal CAS. In the case of the writing cycle, the write enable signal is supplied with the timing equal to the switching of address. Thus the data of the bus AD is written to the memory of the device 2. In such a way, the signal CS is also multiplexed to realize a direct connection between the devices 1 and 2.