To change an output pulse in real time and in response to a trigger signal without increasing the burden of an arithmetic processing unit by inputting a 1st pulse control signal produced based on the 1st pulse control data to a 1st double input logic circuit.

The first trigger signals are inputted to an arithmetic processing unit 1 and a 1st data latch circuit 13 from a trigger circuit 2. The circuit 13 latches a 1st control signal in response to the received trigger signal and controls the output of the control signal at a high level. Thus, a pulse string which varies in the same phase as the pulse train that is outputted from a pulse generation circuit 14 is outputted from a NAND circuit 10 and an output state is secured for an output pulse. At the same time, the unit 1 performs the interrupt processing in response to the first trigger signal and writes the new data into a 1st pulse control register 12. In such a way, the circuit 13 latches the data by the trigger signal.