PURPOSE: To realize high speed arithmetic operation by using an on-chip program and data storage unit, single accumulator, and parallel multiplier.

CONSTITUTION: Microcomputer 10 has a program storage unit 14, a data storage unit 15, and a CPU. The CPU is displaced near two internal buses, a 16-bit program bus P-BUS, and a 16-bit data bus D-BUS. A bus interchange module BIM permits loading of program counter PC from an accumulator Acc, that is, accessing the ROM 14 for the constant through the P-BUS, BIM, and D-BUS. The arithmetic performance is realized by the on-chip program and data storage units 14 and 15, the large single accumulator Acc, and a parallel multiplier M. Special operations and data transfer are defined and executed in the data storage unit 15.