Title:
MICROCOMPUTER
Document Type and Number:
Japanese Patent JPS6037061
Kind Code:
A
Abstract:
PURPOSE:To shorten a processing time, and to execute an operation at high speed by providing an ROM read-out controlling circuit, and fetching an incorporated ROM directly to an executing unit without making it pass through an instruction latch and an instruction decoder, when reading out the contained ROM. CONSTITUTION:In case of reading out an incorporated ROM7, it can be read directly by an executing unit 4 in accordance with a control of an ROM read-out controlling circuit 11, by making the contents of the incorporated ROM7 coincide in advance with an output of an instruction decoder. Therefore, it is unnecessary to make it pass through an instruction latch and a decoder. Also, according to a constitution of an instruction of the ROM7, an instruction and an operand can be fetched simultaneously to the unit 4, and the number of times of an access to an external storage device 1 can be decreased. In this way, when reading out the incorporated ROM, it is fetched directly to the executing unit without making it pass through the instruction latch and the instruction decoder, the processing time is shortened, and the operation can be executed at high speed.
Inventors:
NAKAGAWA KATSUHIKO
Application Number:
JP14537283A
Publication Date:
February 26, 1985
Filing Date:
August 09, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F9/30; G06F15/78; (IPC1-7): G06F15/06
Attorney, Agent or Firm:
Uchihara Shin