To provide a microcontroller capable of preventing erroneous reading of a memory when restarting it and reducing electric power consumption further.

When a stop signal HLT is outputted from a CPU 10, an address signal ADI increased sequentially from an address control part 31 based on an address signal ADR is generated and is given to a ROM 20. The data DAT read sequentially from the ROM 20 in accordance with the address signal ADI is sequentially held in data latches 34 to 36, and then a mode signal MDA for bringing the ROM 20 into a stand-by mode is outputted from the address control part 31. When the stop signal HLT is released, the mode signal MDA is immediately released and the data held in the data latches 34 to 36 are selected by a selector 37 and are sequentially given to the CPU 10 in accordance with the address signal ADR. Consequently, erroneous operation does not occur even if the rise of the ROM 20 is delayed.