Title:
MICROPROCESSOR UNIT
Document Type and Number:
Japanese Patent JP3105693
Kind Code:
B2
Abstract:
PURPOSE: To curtail the circuit scale by constituting the microprocessor unit so that a computing element calculates data of each prescribed bit width by storing it in an arithmetic register by bringing it nearer to the upper bit side of this register.
CONSTITUTION: A flag generating circuit 11 is connected in advance to the uppermost side of an arithmetic register 10, and generates a sign flag, an overflag and a carry flag. A selector 14 switches and transmits carry of a result of operation in a bit of the lower side by one bit from a prescribed bit position, and the carry flag generated by the flag generating circuit 11. This bit position is a bit position lowered to the lower bit side by prescribed bit width except the maximum bit width from the uppermost bit of this arithmetic register 10. In such a state, data of each prescribed width is calculated by storing it in the arithmetic register 10 and bringing it nearer to the upper bit side of its arithmetic register 10. In such a way, by minimizing the number of flag generating circuits 11 and selectors 14 the circuit scale can be curtailed.
Inventors:
Takehito Izumi
Yasuo Yamada
Hiroshi Suzuki
Yasuo Yamada
Hiroshi Suzuki
Application Number:
JP9136193A
Publication Date:
November 06, 2000
Filing Date:
April 19, 1993
Export Citation:
Assignee:
Kawasaki Steel Co., Ltd.
International Classes:
G06F7/38; G06F7/50; G06F7/505; G06F9/305; (IPC1-7): G06F9/305; G06F7/38; G06F7/50
Domestic Patent References:
| JP2230320A | ||||
| JP5843041A |
Attorney, Agent or Firm:
Yoshio Kosugi (2 outside)