To provide a microprocessor that can easily fit to multi-processing and a multi-user environment while maintaining tamper resistance and performance.
A random number generating section 104 generates a random number that cannot be deducted from the outside of the microprocessor 100 at application of power or in the case of resetting and generates a processor transient key Kc depending on the generated random number. A random number storage section 105 stores the processor transient key Kc. When an exception detection section 108 detects an exception state such as interruption and process switching, an arithmetic processing section 103 instructs an encryption processing section 109 to save a context such as values of each register in a register group 102. Accordingly the encryption processing section 109 encrypts the context by using the processor transient key Kc. An external memory 1 stores the encrypted context.
SHIRAKAWA KENJI
HASHIMOTO MIKIO
TERAMOTO KEIICHI
OZAKI SATORU
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