Title:
MICROPROCESSOR
Document Type and Number:
Japanese Patent JP3934710
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To build a DRAM and a cache into a microprocessor that has also an external bus master.
SOLUTION: In a microprocessor 101, a selector 7 is connected to a bus ID (0:127) via a write buffer 5 and also a DRAM 27, a cache 28 and an IQ 8 are connected to the bus ID (0:127). The bus ID (0:127) is connected to the microprocessor 101, an external memory 4 and an external bus master 41 via a data bus D (0:15), where a BIU(bus interface unit) 3 is prepared. The microprocessor 101 is also connected to the memory 4 and the master 41 via an address bus 58 and the control buses 56 and 57. The BIU 3 controls the accesses to a memory containing a microprocessor and also to another memory which is externally connected to the said memory.
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Inventors:
Yukari Takada
Mitsugi Sato
Hirokuni Kondo
Katsunori Sawai
Mitsugi Sato
Hirokuni Kondo
Katsunori Sawai
Application Number:
JP24337496A
Publication Date:
June 20, 2007
Filing Date:
September 13, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F13/36; G06F13/16; G06F13/40; G06F15/78; (IPC1-7): G06F13/36; //G06F15/78
Domestic Patent References:
| JP7028745A | ||||
| JP60189047A | ||||
| JP7121500A | ||||
| JP4162147A | ||||
| JP6324939A | ||||
| JP5324539A | ||||
| JP63303452A |
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita
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