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Title:
MICROPROCESSOR
Document Type and Number:
Japanese Patent JPS6195453
Kind Code:
A
Abstract:

PURPOSE: To improve an interruption processing function by forming a latch circuit for holding an interruption signal inputted from an external terminal and selectively holding the information by a control signal formed by software.

CONSTITUTION: When the output Q of an interruption control register CR corrected to a reset terminal R of the latch circuit FF is supplied, the latch circuit FF holds an edge (EG) detecting output selectively. A specific address is assigned to the register CR and a writing signal D selected by an output A and supplied through a data bus is stored in the address. When '1' is written in the register CR, the circuit FF is forcedly reset by the output Q which is set up to '1' and the reception of an interruption signal from the external terminal is inhibited. On the other hand, '0' is written in the register CR to release the reset of the circuit FF by the output Q which is set up to '0' and receive the interruption signal from the external terminal. The circuit FF constitutes a vector ring generating circuit and the specification of interruption processing and an address to be jumped are specified on the basis of the output of the FF.


Inventors:
ISHIHARA KOJI
Application Number:
JP21617584A
Publication Date:
May 14, 1986
Filing Date:
October 17, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F9/46; G06F9/48; G06F11/00; G06F11/30; G06F15/78; (IPC1-7): G06F9/46; G06F11/00; G06F15/06
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
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