PURPOSE: To improve the performance of a processing device, by introducing the hardware capable of executing the branch instruction to reduce the number of execution steps for the execution of the delay type conditional branch instruction.

CONSTITUTION: The address selecting circuit 38 is controlled to output the forced branch address of micro (μ) instruction register 22 to μ program storage device 21, and the pattern of the branch destination address as the μ instruction word to be executed next is read to μ instruction register 22 and is set to delay branch FF37 simultaneously. Next, the operation specified by execution control field 26 is executed, and FF37 is set or reset according to the operation result. The value of the specified field 31 of the delay type conditional instruction is latched to branch condition selection signal latch circuit 33, and the output of circuit 33 is input to comparing circuit 35. In the next step, contents of specified value field 31 and the operation result which determined the branch condition set in FF37 are compared by comparing circuit 35, and it is checked whether the branch condition is satisfied or not, thus reducing the number of execution steps.