Title:
MIS TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5587485
Kind Code:
A
Abstract:
PURPOSE: To accomplish a shorter channel by projecting the channel into the substrate thicker than the source and the drain.
CONSTITUTION: An n-layer 15 is produced by ion implantation from an opening 21a made through an SiO2 film on a p-type Si. The opening 21a is expanded to form a gate oxide film 21b, and a resit mask 16 is used to selectively form a p+- type poly Si electrode 4 on the central part thereof. Then, n+-type source and drain layers 2 and 3 produced shallower than the channel 15. Then, after the removal of the resist, an SiO2 film is applied and a window is etched to produce electrode wires 18, 19 and 20. This arrangement allows effective avoidance of punch through thereby accomplishing finer FETs.
Inventors:
NISHIUCHI KOUICHI
OKA HIDEKI
OKA HIDEKI
Application Number:
JP16311978A
Publication Date:
July 02, 1980
Filing Date:
December 26, 1978
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L29/78; H01L29/06; (IPC1-7): H01L29/06; H01L29/78