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Patent Searching and Data


Title:
MIS TYPE SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0263116
Kind Code:
A
Abstract:

PURPOSE: To prevent an oxide film from being destroyed during an ion impregnation operation without increasing a production process of a semiconductor integrated circuit by a method wherein a wiring part identical to a gate wiring part is grounded additionally on a pattern.

CONSTITUTION: Resists 4 are connected by using a gate wiring part 3 or a resist 4; the gate wiring part 3 is formed as a lattice pattern along a cutting margin 9, and is brought into contact with a high-conductivity metal ring 10 at edge of a wafer; the metal ring 10 is grounded. A newly added gate wiring part 3 comes into contact with the resist 4 during an ion impregnation operation; an electric charge 6 during the ion impregnation operation is passed through this wiring part 13 and lowers a ground potential by the metal ring 10 at the edge of the wafer.


Inventors:
AOKI AKIHIDE
Application Number:
JP21432388A
Publication Date:
March 02, 1990
Filing Date:
August 29, 1988
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L29/78; H01L21/265; H01L21/336; H01L21/8238; H01L27/092; (IPC1-7): H01L21/265; H01L21/336; H01L27/092; H01L29/784
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)