Title:
SILICON CARBIDE VERTICAL MOSFET AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3206727
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide higher withstand voltage of a vertical MOSFET using SiC.
SOLUTION: A selective ion implantation is performed with phosphorus ion using a wide mask, then a selective ion implantation is performed with boron ion using a narrower mask, and the mask is removed and thermal processing is performed to form a p-base region 33 and n-source region 34. Then a gate oxide film 35 is formed by thermal oxidation, and a gate electrode layer 36 of polycrystal silicon is formed. The length of a channel region 40 is designed independently of the thickness of the p-base region 33, respectively. For example, such structure of high dielectric strength as punch through is avoided in the channel region 40 can be provided. With the use of spacer, especially, the length of channel region 40 is formed with precision, for stable characteristics with good yield.
Inventors:
Katsunori Ueno
Application Number:
JP3608097A
Publication Date:
September 10, 2001
Filing Date:
February 20, 1997
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H01L21/04; H01L21/336; H01L29/12; H01L29/78; (IPC1-7): H01L29/78; H01L21/336
Domestic Patent References:
| JP6151860A | ||||
| JP3141649A |
Attorney, Agent or Firm:
Masaharu Shinobe
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