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Title:
MONITOR SYSTEM FOR PROCESSOR
Document Type and Number:
Japanese Patent JPS55119756
Kind Code:
A
Abstract:

PURPOSE: To easily detect the failure of processor with the count value, by providing the count circuit corresponding to each processor at the control section of common bus, in the processor monitor system of multiprocessor system.

CONSTITUTION: The processors 201...20n are mutually connected via the common bus 10, and the bus 10 is controlled with the bu-control section 100. In the control section 100, the bus start request from the processors 201...20n corresponding to the count circuits 31...3n is detected for start request, and when a signal is inputted to the clear terminal CL of the count circuits 31...3n corresponding to the processor having start request, the count circuit is cleared. If a processor is in failure and no start request is caused, no clear signal is inputted to the clear terminal CL of the count circuit corresponding, and clock pulses more than specified value are inputted, and the signal "1" is outputted from the output terminal OV of the count circuit. Thus, the failure state of the processors 201...20n can easily be detected.


Inventors:
YAMAMOTO MASAHIKO
Application Number:
JP2707679A
Publication Date:
September 13, 1980
Filing Date:
March 08, 1979
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F15/16; G06F11/30; G06F15/177; (IPC1-7): G06F11/30
Domestic Patent References:
JPS5415632A1979-02-05



 
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