PURPOSE: To enable switching at high speed by lowering the current amplification factor hFE of a third transistor.

CONSTITUTION: The ratio of emitter concentration to base one is made far smaller than those of other two transistors Tr1, Tr2 in order to lower the hFE of a third transistor Tr3. On an NPN transistor, a base layer such as one 3' in high concentration is formed on a silicon substrate with layers such as an N+ layer 1 and an N- layer 2 through a selective diffusion method of boron, etc., base layers such as ones 3 in low concentration are formed, and each base layer 3, 3' is pushed in proper depth through push-in diffusion. When preceding push-in is executed before the formation of the base layers in low concentration to further deepen the base layer 3' in the third transistor Tr3 at that time, an effect is further displayed in order to lower hFE. High-concentration emitter layers 4 are shaped, and a low-concentration emitter layer 4' is formed. Contact holes are bored to a surface protective oxide film 5, and metallic electrodes 6 being in contact with element regions through the contact holes are formed.