PURPOSE: To improve universality with the small number of terminals by temporarily storing output information or a signal given to a port, outputting a specified address to an internal bus when the address is given and operating a multiplexer.

CONSTITUTION: A register 17 to control a multiplexer 13, which is composed of transmission gates Q16-Q20, is composed of a latch circuit 17a and a decoder circuit 17b. The signal given from an internal data bus BUS to a port 12 is set through gates Q1-Q3 to the circuit 17a. The output of an A/D conversion circuit 14 is inputted as the output information to a register 16 and the output of the register 16 is also connected through transmission gates Q4-Q6 to a bit line corresponding to the BUS. When the specified address is given to the registers 16 and 17, information for operating the multiplexer 13 are fetched from the BUS and operation is started. An analog input, to which A/D conversion is executed, is made common with a digital input and the universality can be improved with the small number of the terminals.