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Patent Searching and Data


Title:
MOS BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPH0969764
Kind Code:
A
Abstract:

To realize a MOS buffer circuit which has a simple constitution and is easily made into an integrated circuit and has a noise elimination function.

An input signal is directly supplied to respective gates of a PMOS 3-1 and an NMOS 4-2, and the input signal is supplied to respective gates of a PMOS 3-2 and an NMOS 4-1 after being delayed by a delay element 2. In the period when a spike noise having the pulse width within the delay time of this delay element 2 exists, three out of four transistors are certainly turned off, and therefore, an output 5 goes to the high impedance state, and the just preceding output level is kept, and as the result, the noise is masked.


Inventors:
HOKIMOTO TAKEHIRO
Application Number:
JP22493695A
Publication Date:
March 11, 1997
Filing Date:
September 01, 1995
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
H03K17/16; H03K17/687; (IPC1-7): H03K17/16; H03K17/687
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)