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Patent Searching and Data


Title:
MOS IC DEVICE
Document Type and Number:
Japanese Patent JPS60103675
Kind Code:
A
Abstract:

PURPOSE: To obtain the titled device of high resistance to radiation by making it difficult to cause MOS inversion by prevention of the accumulation of positive residual space charges under a field oxide film by a method wherein the conductor arranged around a MOS transistor is connected to the minimum potential in this device or to a potential based on it.

CONSTITUTION: The titled device has e.g. a poly Si 9 the same as in the gate arranged around the N-channel MOS transistor, and this poly Si is connected to the minimum potential of the semiconductor device from an arbitrary position in design. Such an arrangement of poly Si does not allow the accumulation of positive residual space charges to occur because an electric field does not reach the field oxide film 5 even when an Al wiring 10 is laid out on this oxide film, and MOS inversion does not occur.


Inventors:
OOUCHI MASAHIRO
KUME TOORU
KITAMURA YOSHINARI
Application Number:
JP21178183A
Publication Date:
June 07, 1985
Filing Date:
November 11, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L27/08; H01L21/76; H01L23/552; H01L29/78; (IPC1-7): H01L21/76; H01L27/08; H01L29/40
Attorney, Agent or Firm:
Uchihara Shin