Title:
【発明の名称】増幅回路
Document Type and Number:
Japanese Patent JP3162732
Kind Code:
B2
Abstract:
A differential pair (N1, N2) having an input terminal (3) and an output terminal (4) is coupled to a current mirror (P1, P2) in which a first level shifting circuit (6) and a second level shifting circuit (7) stabilize the d.c. voltage levels on the mutually coupled main electrodes of the differential pair (N1, N2) and the current mirror (P1, P2) respectively. Consequently, the influence of the Early-effect on the differential pair (N1, N2) is suppressed and an improved linear signal transmission from the input terminal (3) to the output terminal (4) is obtained. The level shifting circuit (6) likewise realises a base current compensation for obtaining a high input impedance and the second level shifting circuit (7) realises a base current compensation for equal adjusting currents through the differential pair (N1, N2) to reduce the offset voltage.
Inventors:
Willem Daher
Etze Argen de Boel
Etze Argen de Boel
Application Number:
JP8123391A
Publication Date:
May 08, 2001
Filing Date:
March 22, 1991
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H03F3/34; H03F1/32; H03F3/45; H03F3/50; (IPC1-7): H03F3/45
Domestic Patent References:
| JP5111347A | ||||
| JP54112146A | ||||
| JP54137263A | ||||
| JP564905A | ||||
| JP2146808A |
Other References:
【文献】米国特許3619798(US,A)
【文献】Electronics Vol.40 No.15(1967.07.24)”MOS FET amplifier provides almost infinite impedance”Thomas H.Lynch pp.88
【文献】Electronics Vol.40 No.15(1967.07.24)”MOS FET amplifier provides almost infinite impedance”Thomas H.Lynch pp.88
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)