Title:
STRUCTURE AND MANUFACTURING METHOD OF SPLIT GATE FLASH MEMORY
Document Type and Number:
Japanese Patent JP3211001
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To relax the generation of a point angle structure by a method wherein the title structure is provided with the first and second conductive layers to be isolated from each other by the isolating action of the second and third isolation.insulating layers whereon the first and second conductive layers are formed.
SOLUTION: The first conductive layer 3 is formed above the local region 21 of the first isolation.insulating layer 2 while the second isolation.insulating layer 4 is overlapped on the other local regions 22 as well as on the right and left sidewalls of the first conductive layer 3. Besides, the third isolation.insulating layer 5 is formed above the first conductive layer 3 while the second conductive layer 6 formed above the second and third isolation insulating layers 4, 5 is mutually isolated from the first isolation.insulating layer 3 by the isolating action of the second and third isolation.insulating layers 4, 5 to be used as a control gate. In such a constitution, the production of the pointed angle effect on the right and left ends of the first conductive layer 3 can be lessened by the third isolation.insulating layer 5 formed above the right and left sidewall oxide layers 41, 42.
Inventors:
Song Country Building
Application Number:
JP33564096A
Publication Date:
September 25, 2001
Filing Date:
December 16, 1996
Export Citation:
Assignee:
Taiwan Shigei Electronic Electronics Co., Ltd.
International Classes:
G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; G11C16/04; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP227773A | ||||
| JP4176172A | ||||
| JP62131582A | ||||
| JP5267684A | ||||
| JP5536928A | ||||
| JP8236649A | ||||
| JP8236647A |
Attorney, Agent or Firm:
Eiji Saegusa (2 others)