Title:
MULTI COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPS5585964
Kind Code:
A
Abstract:
PURPOSE:To increase the processing ability of multi computer system, by constituting the memory unit possible for random access with the random shift register RSR and connecting the output of one RSR to the input of another RSR. CONSTITUTION:One serial output SO of the memory unit consisting of RSR15-1, 15-2 and another serial input SI are connected with the copy buses 18-1, 18-2. In transfering the content of the memory unit 15-1 at muPC 17-1 to the memory unit 15-2 at muPC 17-2, the content of the unit 15-1 is sequentially transferred to the unit 15-2 via the bus 18-1 by taking the logic of the control input C of the unit 15-2 as 0. During the period of data transfer, the muPC 17-1 can access the memory unit freely via the bus 16-1. The transfer of the content of the unit 15-2 to the unit 15-1 is similarly made by taking the logic of the control input of the unit 15-1 as 0. Accordingly, the data transfer outside the computer system and the access in the system can simultaneously be made.
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Inventors:
OOTSUYAMA MINORU
Application Number:
JP15955378A
Publication Date:
June 28, 1980
Filing Date:
December 21, 1978
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F15/16; G06F3/00; G06F12/00; G06F13/00; G06F13/12; G06F13/16; (IPC1-7): G06F3/00; G06F13/00; G06F15/16