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Title:
マルチコアシステム、マルチコアシステムの制御方法及びプログラム
Document Type and Number:
Japanese Patent JP5375650
Kind Code:
B2
Abstract:

To suppress degradation in image-sound synchronization accuracy, while suppressing the load on a reservation system, and to prevent sound break.

A multi-core system 2 includes a main system program 610 which operates in a processor core 61 and stores a mixed synthesized speech data into a buffer 63 for DMA (direct memory access) transfer; a reserved system program 620 which operates in a processor core 62; and a voice output part 64, which sequentially stores and reproduces the synthesis speech data transferred from the buffer 63 for DMA transfer. The reserved system program 620 sets a timer, according to reception of DMA transfer end interrupt request. When the timer is timed out, the reserved system program determines whether, a storage amount of a synthesis speech data of the buffer 63 for DMA transfer reaches a predetermined data amount; and when it does not reach the predetermined data amount, the reserved system program succeeds and executes mixing and storing of the synthesis speech data executed by the main system program 610.

COPYRIGHT: (C)2011,JPO&INPIT


Inventors:
Shotaro Kono
Kentaro Sasakawa
Application Number:
JP2010030143A
Publication Date:
December 25, 2013
Filing Date:
February 15, 2010
Export Citation:
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Assignee:
NEC
International Classes:
G06F11/20; G06F13/38; G10L19/00
Domestic Patent References:
JP2004004163A
JP2008292755A
Attorney, Agent or Firm:
Ken Ieiri