Title:
積層水平アクティブストリップに配置され、垂直制御ゲートを有するマルチゲートＮＯＲフラッシュ薄膜トランジスタストリング
Document Type and Number:
Japanese Patent JP6800964
Kind Code:
B2
Abstract:
Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
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Inventors:
Harari, Eri
Application Number:
JP2018517296A
Publication Date:
December 16, 2020
Filing Date:
July 27, 2016
Export Citation:
Assignee:
Sunrise Memory Corporation
International Classes:
H01L27/11582; H01L21/336; H01L27/11573; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP2010251572A |
Foreign References:
| KR1020120085603A | ||||
| US20170077118 |
Attorney, Agent or Firm:
Patent business corporation Oshima patent office