Title:
MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION
Document Type and Number:
Japanese Patent JP2013157077
Kind Code:
A
Abstract:
To provide an access buffer, such as a page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation.
The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.
Inventors:
PYEON HONG BEOM
Application Number:
JP2013108569A
Publication Date:
August 15, 2013
Filing Date:
May 23, 2013
Export Citation:
Assignee:
MOSAID TECHNOLOGIES INC
International Classes:
G11C16/06; G11C16/02; G11C16/04
Domestic Patent References:
| JP2007012241A | 2007-01-18 | |||
| JP2007042265A | 2007-02-15 | |||
| JP2007026631A | 2007-02-01 | |||
| JP2006331614A | 2006-12-07 | |||
| JP2006277786A | 2006-10-12 | |||
| JP2006172630A | 2006-06-29 | |||
| JP2006172523A | 2006-06-29 | |||
| JP2001325796A | 2001-11-22 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Masatake Shiga
Takashi Watanabe
Keiji Kiuchi
Masatake Shiga
Takashi Watanabe
Keiji Kiuchi
Previous Patent: ENHANCED PROGRAMMING AND ERASURE SCHEMES FOR ANALOG MEMORY CELLS
Next Patent: CONTROL DEVICE FOR INFORMATION PROCESSING DEVICE
Next Patent: CONTROL DEVICE FOR INFORMATION PROCESSING DEVICE