Title:
マルチレベルインバータ
Document Type and Number:
Japanese Patent JP5824111
Kind Code:
B2
Abstract:
A multilevel inverter having a configuration adequate to enhance efficiency while reducing conduction loss is disclosed, the multilevel inverter including a rectifier, a smoothing unit and an inverter unit, wherein
the inverter unit includes a first switch unit interposed between the first node and a first output terminal, second switch units interposed between the second node and the first output terminal, a third switch unit interposed between the third node and the first output terminal, a fourth switch unit interposed between the first node and a second output terminal, fifth switch units interposed between the second node and the second output terminal and a sixth switch unit interposed between the third node and the second output terminal.
Inventors:
Yuanno
Application Number:
JP2014116803A
Publication Date:
November 25, 2015
Filing Date:
June 05, 2014
Export Citation:
Assignee:
LSIS CO.,LTD.
International Classes:
H02M7/49; H02M7/487
Domestic Patent References:
| JP2007221987A | ||||
| JP2001045772A | ||||
| JP2002247862A | ||||
| JP2000184720A | ||||
| JP2013078204A | ||||
| JP2006320103A | ||||
| JP2014128154A |
Foreign References:
| WO2012025978A1 | ||||
| US20090045782 | ||||
| US5625545 |
Attorney, Agent or Firm:
Atsushi Aoki
Jun Tsuruta
Tomohiro Minamiyama
Akira Kawai
Kenichi Nakamura
Jun Tsuruta
Tomohiro Minamiyama
Akira Kawai
Kenichi Nakamura