Title:
MULTI-PROCESSOR SYSTEM AND ITS TEST METHOD
Document Type and Number:
Japanese Patent JPH01134536
Kind Code:
A
Abstract:
PURPOSE:To load the test programs into all processors with high efficiency by connecting a test ROM to a main processor only and loading the data on the main processor to other processors. CONSTITUTION:For a main processor board 1 connected with a test board 11, an instruction of a test ROM 16 is given to a processor 12 together with the test programs of all processors are stored in a DRAM 15 at application of a power supply. Other processors fetch the instructions of a boot ROM via a system bus 4. Such a program is set into the boot ROM so that the processors except a main processor are kept waiting until the test programs are loaded into their own local memories. As a result, the test programs are automatically loaded into all processors.
Inventors:
YONEKURA MIKIO
Application Number:
JP29269687A
Publication Date:
May 26, 1989
Filing Date:
November 19, 1987
Export Citation:
Assignee:
FANUC LTD
International Classes:
G06F11/16; G05B15/02; G05B19/04; G05B19/048; G05B19/05; G05B19/414; G05B23/02; G06F15/16; G06F15/177; (IPC1-7): G05B15/02; G05B19/04; G05B19/403; G05B23/02; G06F11/16; G06F15/16
Attorney, Agent or Firm:
Minoru Tsuji
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