PURPOSE: To quickly transfer fault information mutually without allowing it to pass through a system bus by constituting the system so that the fault information is transferred directly to an other processor by a fault information control circuit.
CONSTITUTION: When it is decided that detected abnormality is a serious fault, a CPU 211 commands its fact to a fault information control circuit 217, and the fault information control circuit 217 outputs a fault signal to a signal line 10 through a driver 218. In this regard, a CPU 311 also executes the same processing. A fault information control circuit 317 of a CPU board 31 side always monitors the signal line 10 through a receiver 319, therefore, can detect a fault signal of a CPU board 21 side, and when the fault signal is detected, a fact that a serious fault is generated in the CPU board 21 side is informed to the CPU 311. Accordingly, the CPU 311 can recognize fault information related to the CPU board 21, and can execute quickly the countermeasure processing to the fault. In this regard, a fault information control circuit 217 of the CPU board 21 side also execute the same processing.
WO/2000/069169 | DEVICE FOR PROCESSING DIGITAL IMAGE DATA |
WO/2019/166862 | CLIQUE SERVICE IN CLOUD |
JPS58103061 | CALCULATION SYNCHRONISM RESTORING SYSTEM |
JPH02281368A | 1990-11-19 | |||
JPS60252962A | 1985-12-13 |