Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
薄膜トランジスタのための多段階CVD法
Document Type and Number:
Japanese Patent JP4018625
Kind Code:
B2
Abstract:
An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiNx at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon. The process is applicable to either the back channel etched TFT device or the etch stopped TFT device.

Inventors:
Come S. Law
Robert Robertson
Michael corlac
Angela Tee Lee
Takako Takehara
Guoff Jeff Fen
Dan Maidan
Application Number:
JP2003413631A
Publication Date:
December 05, 2007
Filing Date:
December 11, 2003
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H01L21/205; C23C16/24; C23C16/34; H01L21/31; H01L21/318; H01L21/336; H01L29/786
Domestic Patent References:
JP2025074A
JP5299657A
JP61051878A
Attorney, Agent or Firm:
Yoshiki Hasegawa
Yuichi Yamada
Yasuhito Suzuki