Title:
MULTICHANNEL ECHO CANCELER
Document Type and Number:
Japanese Patent JP3230662
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multi channels echo canceler with a simplified hardware that can efficiently perform echo processings of many channels.
SOLUTION: An estimation processing circuit 300 has an adaptive finite impulse response(FIR) filter 310 to selectively perform estimation processing of each channel and updating of a filter coefficient. An estimation channel selection circuit 400 selects a channel to be estimated on the basis of an estimation request supplied by an estimation operation judgment circuit 134 of an echo canceler circuit 130 and of the degree of stability of the estimation processing of the echo canceler circuit 130. Then, the estimation processing circuit 300 performs estimation processing with regard to the echo canceler circuit 130 of a selected channel and supplies an FIR filter 132 of the echo canceler circuit 130 with the updated filter coefficient. Thus, echo estimation processing by each echo canceler circuit 130 is performed by time-division.
Inventors:
Atsushi Hasegawa
Application Number:
JP7672998A
Publication Date:
November 19, 2001
Filing Date:
March 09, 1998
Export Citation:
Assignee:
NEC
International Classes:
H03H21/00; H04B3/23; (IPC1-7): H04B3/23; H03H21/00
Domestic Patent References:
| JP287861A | ||||
| JP6197050A | ||||
| JP6318845A | ||||
| JP51144111A | ||||
| JP923173A |
Attorney, Agent or Firm:
Shigeru Noda