Title:
MULTILAYER CERAMIC CAPACITOR
Document Type and Number:
Japanese Patent JP2022114215
Kind Code:
A
Abstract:
To provide a multilayer ceramic capacitor which is reduced in ESR.SOLUTION: A multilayer ceramic capacitor 1 includes: a laminate 2 including dielectric layers 14 and internal electrode layers 15 which are alternately laminated; and external electrodes 3 arranged on both end faces C of the laminate 2 in a longitudinal direction L, respectively, and connected to the internal electrode layers 15. In a LT cross section at the center in a width direction W, each external electrode 3 has, alternately in a lamination direction T, a first part 31 which is arranged at a part on the end face C where the internal electrode layer 15 extending to an external electrode 3 side is located, and a second part 32 which is arranged at a part on the end face C where the dielectric layer 14 is located. The first part 31 has a first inner part 31in on an end face C side and a first outer part 31ou outside the first inner part 31in. The second part 32 has a second inner part 32in on the end face C side and a second outer part 32ou outside the second inner part 32in. The density of Si in the first inner part 31in is lower than the density of Si in the second inner part 32in.SELECTED DRAWING: Figure 4
Inventors:
KOBAYASHI HARUKI
Application Number:
JP2021010417A
Publication Date:
August 05, 2022
Filing Date:
January 26, 2021
Export Citation:
Assignee:
MURATA MANUFACTURING CO
International Classes:
H01G4/30
Attorney, Agent or Firm:
Ryuta Kato
Tetsuo Shiba
Tetsuo Shiba