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Patent Searching and Data


Title:
MULTILAYER CIRCUIT BOARD AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2005085921
Kind Code:
A
Abstract:

To provide a highly reliable multilayer circuit board in which the connection reliability of a via for connecting interlayer wiring layers electrically is enhanced, and to provide its manufacturing method.

In a multilayer circuit board having two or more wiring layers formed on one side or both sides of an insulating substrate 11 through an insulation layer and connected through vias, the via is formed by providing a truncated cone conductor formed on a land, a bump conductor becoming the via formed on the recess of the land and a bump conductor becoming the via formed on a ring land. Consequently, adhesion is enhanced between the bump conductor and the land, and the formation of an insulating resin layer during production of the multilayer circuit board and separation of the bump conductor from the land during stripping process are eliminated resulting in a highly reliable multilayer circuit board in which connection reliability of via connecting interlayer wiring layers electrically is enhanced.


Inventors:
SEKINE HIDEKATSU
Application Number:
JP2003315100A
Publication Date:
March 31, 2005
Filing Date:
September 08, 2003
Export Citation:
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Assignee:
TOPPAN PRINTING CO LTD
International Classes:
H05K1/11; H05K3/46; (IPC1-7): H05K3/46; H05K1/11
Domestic Patent References:
JP2001068858A2001-03-16
JP2001185653A2001-07-06
JP2001007529A2001-01-12
JP2002246753A2002-08-30