To reduce the generation of defective due to entering of a plating solution into a multilayer circuit board.

The multilayer circuit board is provided with a dielectric substrate 10 consisting of a plurality of dielectric layers 11-14, pad electrode patterns 21, 22 formed on surfaces 10a, 10b of a dielectric substrate 10 respectively, and an opposite electrode pattern 20a formed in the inside of the dielectric substrate 10. The pad electrode patterns 21, 22 are connected to internal electrodes 20 not like a direct current, but like high frequency by capacitive coupling to the opposite electrode pattern 20a via the dielectric layer 11 or 14. With this configuration, since the number of vias to be formed on the dielectric layers 11 or 14 positioned on the lowermost layer or uppermost layer can be reduced, the plating solution can be prevented from entering through the vias, and corrosion due to entering of the plating solution can be efficiently prevented.