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Patent Searching and Data


Title:
MULTILAYER INTERCONNECTION
Document Type and Number:
Japanese Patent JPS6215834
Kind Code:
A
Abstract:

PURPOSE: To flatten the irregularities on a multilayer interconnection, to prevent damage due to the dry etching of electrodes and to decrease wiring resistance, by providing a metal film of a good conductor at least at a part on the lower wiring layer of the connecting part of the lower wiring layer and an upper wiring layer, and leveling the thickness of the lower wiring layer.

CONSTITUTION: An SiO2 interlayer insulating film 30 is leveled by an etch back method, and a flat interlayer insulating film 44 is formed. Then, a through hole is formed at the connecting part of a first wiring layer 20 and the upper wiring layer by a dry etching method. Then, a gold film 60 corresponding to the depth of the through hole (thickness of the interlayer insulating film 44) is deposited by a vacuum evaporation method. Thereafter, a mask made of a photoresist film is provided again, and a through hole is formed in the interlayer insulating film 44 on a wiring 30 by dry etching. Then, as wiring metal for an upper layer (second layer), e.g., titanium-gold (Ti-Au) is deposited on the entire surface. Thus second wiring layers 70 and 80 are formed. Since the gold, which is a good conductor, is provided at the connecting part of the upper wiring layer 70 and the lower wiring layer 20 by 0.7μm, the thickness of the lower wiring layer is leveled.


Inventors:
ISHIKAWA MASAOKI
Application Number:
JP15411685A
Publication Date:
January 24, 1987
Filing Date:
July 15, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/3205; (IPC1-7): H01L21/88
Domestic Patent References:
JPS5848438A1983-03-22
JPS6098654A1985-06-01
JPS614244A1986-01-10
JPS60136336A1985-07-19
Attorney, Agent or Firm:
Yoshiyuki Iwasa