Title:
MULTILAYER WIRING SUBSTRATE
Document Type and Number:
Japanese Patent JP3798978
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce influence from crosstalk noise and EMI noise in a multilayer wiring substrate having an orthogonal parallel wiring group.
SOLUTION: The multilayer is provided with a laminated wiring board. The wiring board comprises a first parallel wiring group L1 which is formed on a first insulation layer (13), and each proceeds to a point of intersection in predetermined each section area; a second parallel wiring group L2 which is formed on a second insulation layer (14) laminated on the first insulation layer (13), and is each orthogonal to the first parallel wiring group L1 in each section area; and a through conductor group T for electrically connecting them. The first parallel wiring group L1 has an earth wiring G1 in each section area and is encircled by a circular earth wiring GR formed on the periphery of the first insulation layer (13), and the earth wiring G1 is electrically connected to the circular earth wiring GR such that a wiring at the outermost wiring of the second parallel wiring group L2 is an earth wiring G2. The circular earth wiring GR allows reducing an influence from EMI noise.
Inventors:
Shougen Masahisa
Application Number:
JP2001395103A
Publication Date:
July 19, 2006
Filing Date:
December 26, 2001
Export Citation:
Assignee:
Kyocera Corporation
International Classes:
H05K3/46; H05K1/02; (IPC1-7): H05K3/46
Domestic Patent References:
| JP652170U | ||||
| JP327564A |