Title:
MULTIOUTPUT POWER CIRCUIT FOR LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3590335
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multioutput power circuit capable of preventing the latch-up of a logic circuit with a simple configuration.
SOLUTION: This circuit has a configuration having at least one DC voltage converter and connecting a resistor between the input terminal and output terminal of that DC voltage converter. By inserting the resistor between the input terminal and output terminal of the DC voltage converter, an output voltage rises simultaneously with rising of an input voltage. Since plural output power supply voltages simultaneously rise, the latch-up of the logic circuit is prevented.
Inventors:
Yoshimi Kokufuda
Application Number:
JP2000258397A
Publication Date:
November 17, 2004
Filing Date:
August 29, 2000
Export Citation:
Assignee:
ALLIED TELESIS HOLDINGS K.K.
International Classes:
H02J1/00; G05F1/00; G05F1/56; G06F1/26; (IPC1-7): G06F1/26; H02J1/00
Domestic Patent References:
| JP6298383A | ||||
| JP2000184694A |
Attorney, Agent or Firm:
Yuji Katsuragi