Title:
MULTIPLE CHOICE OUTPUT INHIBITOR
Document Type and Number:
Japanese Patent JP3488655
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve reliability by constituting multiple choice output propriety decision depending upon the decision of an operator of a logical circuit and eliminating a mistake on the decision of the operator.
SOLUTION: The multiple choice output inhibitor has an adder 1 inputting and adding a plurality of operating outputs states or a plurality of actual-output states, an equivalent decision device 2 deciding whether or not operating output states or actual output states are the equivalent, a logical integrator 3 logically adding an output from the equivalent decision device 2 and using the result of addition as a digital-signal output-enabling condition (d), a reset priority flip-flop setting an operating state by the digital-signal output-enabling condition (d) and a condition in which a master relay is not turned on, and a delay circuit delaying and outputting an output signal from the reset priority flip-flop. When the condition of the operating output only at one point and the condition of no actual output simultaneously hold, the output-enabling state of a digital signal is decided, and both conditions can be used as the output conditions of the actual output.
Inventors:
Kitajima Hideki
Application Number:
JP8355599A
Publication Date:
January 19, 2004
Filing Date:
March 26, 1999
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H02H11/00; H02J1/00; (IPC1-7): H02J1/00; H02H11/00
Domestic Patent References:
| JP4284099A | ||||
| JP5481483A | ||||
| JP59117894A | ||||
| JP6157196A | ||||
| JP61219288A |
Attorney, Agent or Firm:
Norio Ogo (1 outside)
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