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Title:
MULTIPLE INFORMATION PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPS57729
Kind Code:
A
Abstract:

PURPOSE: To reconstitute a multiprocessor even when one CPU is troubled by providing each of CPUs, sharing a main storage device, with two pairs of input and output ports for a loop interface and by alternating the return flow directions of information in response to a control signal.

CONSTITUTION: Central processing units CPU0WCPU2 are connected in a loop and use a main storage device MS in common. In triple multiple operation, each CPU normally uses the connection ports of the input port I1 and output port O1 of a loop interface IF for operation to circulate information, required among the CPUs, in a loop shape. For example, if the CPU0 is troubled, the CPU1 uses the connection ports of the input port I2 and output port O1 of the loop IF by being switched by a system constitution controlling signal, and the CPU2 uses the connection ports of the input port I1 and output port O2, thereby circulating informatin between the CPU1 and CPU2 in the loop shape.


Inventors:
MATSUURA TSUGUO
Application Number:
JP7395980A
Publication Date:
January 05, 1982
Filing Date:
June 02, 1980
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F13/14; G06F3/00; G06F11/20; G06F13/00; G06F15/16; G06F15/177; (IPC1-7): G06F3/00; G06F11/20; G06F15/16