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Title:
MULTIPLEXER AND INVERSE MULTIPLEXER
Document Type and Number:
Japanese Patent JP2003008443
Kind Code:
A
Abstract:

To provide a multiplexer that avoids a word alignment device of a serial parallel converter from being malfunctioned by a K28.5 code included in the lower-order 10-bits when multiplexing a plurality of gigabit Ethernet signals.

The gigabit Ethernet signals 3a, 4a are fed to optical transceivers 11, 12, serial parallel circuits 13, 14, and elastic smoothers 15, 16, where the clock speed is adjusted. A code swapper 17 preserves only the K28.5 signal of the uppermost gigabit Ethernet signal, converts the K28.5 signals of the other gigabit Ethernet signals into other code and gives the result to a serial parallel converter 18, which outputs the code as a multiplex signal. In the case of decoding the multiplex signal, the above mentioned other code is converted into the K28.5 signal.


Inventors:
OTA TAKESHI
Application Number:
JP2001189084A
Publication Date:
January 10, 2003
Filing Date:
June 22, 2001
Export Citation:
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Assignee:
PHOTONIXNET CORP
International Classes:
H03M7/14; H03M9/00; H04J3/00; H04J3/04; H04J3/06; H04L25/49; (IPC1-7): H03M7/14; H03M9/00; H04J3/00; H04L25/49
Attorney, Agent or Firm:
Toshio Sawada