Title:
モンゴメリ法による乗算剰余計算装置
Document Type and Number:
Japanese Patent JP3616897
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a calculation device which simplifies the constitution of a product sum circuit and permits pipeline processing and uses a Montgomery algorithm to quickly perform multiplication remainder calculation. SOLUTION: A product sum circuit 21 multiplies outputs of an A register 3 and a B register 4 and adds outputs of a c3 register 26 and a Y register 5 to the multiplication result. A product sum circuit 22 multiplies outputs of an N register 7 and an m register 8 and adds outputs of a c4 register 29 and the product sum circuit 21 to the multiplication result. Registers 26 and 29 for carry in two product sum circuits 21 and 22 are provided independently of each other, and carry is returned to the corresponding product sum circuit. All the processing is performed in a processing unit (k bits). The next operation of the product sum circuit 21 can be performed during the operation of the product sum circuit 22.
Inventors:
Masahiko Takenaka
Koichi Ito
Naoya Torii
Koichi Ito
Naoya Torii
Application Number:
JP1468198A
Publication Date:
February 02, 2005
Filing Date:
January 27, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F7/72; G09C1/00; H04L9/30; (IPC1-7): G09C1/00; G06F7/72
Other References:
ANALYZING AND COMPARING MONTGOMERY MULTIPLICATION ALGORITHMS,EEE Micro,Vol.16, No.3,p.26-33
Attorney, Agent or Firm:
Nobuo Kono