Title:
MULTIPLIER CIRCUIT
Document Type and Number:
Japanese Patent JPS5831472
Kind Code:
A
Abstract:
The invention relates to an improved voltage control amplifier of the type comprising a gain cell. The gain cell is of the type that includes at least one log transistor for each polarity of input signal and at least one antilog transistor for each log transistor, means for algebraically summing a control signal with the log signal provided by each log transistor and means for providing a symmetry adjust signal to the base of a selected transistor of the cell so that the cell provides substantially the same gain for each polarity of input signal when the control signal level is set for zero. The improvement comprises means for generating a correction signal as a function of the control signal level so as to substantially correct for differences between the early effects exhibited by said transistors as said control signal varies and means for applying the correction signal to the base of one the transistors.
Inventors:
DEBITSUTO AARU UERANDO
Application Number:
JP4808182A
Publication Date:
February 24, 1983
Filing Date:
March 25, 1982
Export Citation:
Assignee:
DBX
International Classes:
G06G7/163; G06G7/24; H03G3/32; (IPC1-7): G06G7/163
Attorney, Agent or Firm:
Asamura Akira