PURPOSE: To perform the partial product addition in a multiplication at high speed by preventing the carry by a rounding decision and the carry from an intermediate bit to an upper bit from being generated at the same time.

CONSTITUTION: A system is composed of a partial product generation circuit 136, a preservation adder 100, a carry calculation circuit 101, a sticky calculation circuit 102, an intermediate bit adder A 103, an intermediate bit adder B 104, an upper bit adder 105, an all 1 calculation circuit 106, a rounding decidion circuit A 108, a rounding decision circuit B 109, a selector 110 and an addition result selection circuit 112. At this stage, a case where the carry from a lower bit exists and the carry is generated from the intermediate bit to the upper bit for the first time and a case where the carry due to a rounding decision is generated are made to be prevented from being generated at the same time. Therefore, in the selection of the addition result of the upper bit, the addition result of the upper bit adder 105 by the OR of these two carries or a value where 1 is added to the least significant bit of the addition result of the upper bit adder 105 is selected.