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Title:
MULTIPLYING CIRCUIT OF FREQUENCY AND COMB LINE FILTER USING IT
Document Type and Number:
Japanese Patent JPS5913417
Kind Code:
A
Abstract:

PURPOSE: To obtain a multiplied output with stable frequency which is prevented from modulation due to a period by providing the titled filter with a charge transfer type delay element to be driven by a clock generated from a frequency multiplying circuit and adding or subtracting an input signal to the charge transfer type delay element to/from the delayed signal of the input signal.

CONSTITUTION: The system consists of the frequency multiplying circuit provided with n-1 [(n) is a multiplying number] voltage controlling circuit groups 2, 2', 2" having equal delay time to control time and a control circuit having the frequency equal to 1/2n the repeating period of an input signal, and the comb line filter using the charge transfer type delay element to be driven by a clock generated from the frequency multiplying circuit as its delay element. The outputs 1, 2 of impedance converting buffers 5, 6 are equal to the outputs 1', 2' of a two-phase pulse generating circuit 4. Two clocks 1 and 2 are compared at mutual duty ratios by a duty ratio comparator 7 and an output corresponding to the difference is generated from an output terminal 8 of the comparator 7. The output is smoothed by a capacitor 9, applied to a voltage control delay circuit 2 as control DC voltage and the delay time is controlled. Thus, the delay time adjusting operation is executed so that the duty ratios of the clocks 1, 2 are made equal.


Inventors:
KIMURA TAKESHI
Application Number:
JP12357282A
Publication Date:
January 24, 1984
Filing Date:
July 14, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K5/00; (IPC1-7): H03H15/02; H03K5/00
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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