Title:
MULTIPROCESSOR CONTROLLER
Document Type and Number:
Japanese Patent JPH01236383
Kind Code:
A
Abstract:
PURPOSE:To obtain a multiprocessor effective for real-time processing, in which the bit width of an instruction is not need to be extended, and instructions for respective arithmetic operation parts can be given without any delay by providing control memories to previously store respective primary instruction codes decoded by an instruction decoder in areas corresponding to respective data processing parts. CONSTITUTION:Program data read from a program memory 100 are supplied to an instruction decoder 200 in an LSI and decoded. The decoded instruction code is stored in a control memory 300. The control memory 300 has instruction code storing areas M1-Mn inherent in the respective processing parts correspondingly to plural data processing parts DP1-DPn in the LSI. Namely, the instructions of respective arithmetic processing parts (for example, a multiplication, an addition, a comparison, etc.,) are previously prepared for the control memory 300. Thus, prescribed processing can be obtained immediately by starting the data processing parts DP1-DPn by a flag, a synchronizing signal, etc., without accessing the program memory 100.
Inventors:
ENAMI KAZUMASA
YAGI NOBUYUKI
YAJIMA RYOICHI
KANAI KIYOMASA
MIKAMI SHIGEMI
SASAKI NOBUYUKI
HOSHINO KOJI
HARUKAWA KAZUHIRO
YAGI NOBUYUKI
YAJIMA RYOICHI
KANAI KIYOMASA
MIKAMI SHIGEMI
SASAKI NOBUYUKI
HOSHINO KOJI
HARUKAWA KAZUHIRO
Application Number:
JP6198888A
Publication Date:
September 21, 1989
Filing Date:
March 17, 1988
Export Citation:
Assignee:
JAPAN BROADCASTING CORP
TOSHIBA CORP
TOSHIBA CORP
International Classes:
G06F9/28; G06F9/22; G06F9/38; G06F15/16; G06F15/177; G06T1/20; H04N5/262; (IPC1-7): G06F9/28; G06F9/38; G06F15/16; G06F15/66; H04N5/262
Domestic Patent References:
| JPS556601A | 1980-01-18 |
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)