Title:
マルチプロセッサシステム
Document Type and Number:
Japanese Patent JP4170080
Kind Code:
B2
Abstract:
Disclosed is a multiprocessor system in which even if contention occurs when a common memory is accessed from each of a plurality of processors, the number of times the common memory is accessed is capable of being reduced. The common memory of the multiprocessor system is provided with a number of data areas that store data and with a control information area that stores control information indicating whether each of the data areas is in use, and each processor is provided with a storage unit equivalent to the common memory and with an access controller. The access controller of a processor that does not have access privilege monitors data and addresses that flow on the common bus, accepts data written to the common memory and data read from the common memory, and stores this data in the storage unit of its own processor, thereby storing content identical with that of the common memory.
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Inventors:
Hirokazu Matsuura
Takao Murakami
Kazuya Uno
Takao Murakami
Kazuya Uno
Application Number:
JP2002345371A
Publication Date:
October 22, 2008
Filing Date:
November 28, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/08; G06F9/46; G06F9/52; G06F12/00; G06F12/06; G06F15/167; G06F15/177
Domestic Patent References:
| JP6208547A | ||||
| JP3271859A | ||||
| JP2003316753A | ||||
| JP2001222466A | ||||
| JP8320828A | ||||
| JP5298265A | ||||
| JP5143454A | ||||
| JP3232051A | ||||
| JP3164963A | ||||
| JP2041535A | ||||
| JP60000563A | ||||
| JP57111896A |
Attorney, Agent or Firm:
Chimitsu Saito