PURPOSE: To attain high speed transmission economically without any fault and any complicated circuit configuration by reading a video signal of a receiver side data processing circuit based on a clock.

CONSTITUTION: When video data V whose head is added with a clock generating signal Vc are sent as a serial signal to a receiver side from one transmission line L, the data is fetched by a clock generating section 4, which generates a clock synchronously with the clock CLK sent from the sender based on the head bit signal Vc, and the generated clock CLK is fed to a shift register 5 in matching with the transmission timing of the video signal V1 sent succeedingly. After the video signal V1 is registered in the shift register in the unit of one scanning line or one block synchronously with the clock CLK, the data are latched in a latch circuit 6 based on a latch signal. Simultaneously a latent image is written onto a photosensitive drum (not shown) while an LED head is subject to on/off control with a driver 7 subject to drive control in response to a CPU signal from the circuit 6 based on a strobe signal from a one-shot multicircuit (not shown).