PURPOSE: To provide a manufacturing method that realizes highly integrated devices.

CONSTITUTION: A second interlayer insulating film 14 at a first metallic wiring layer 13 is formed on a first interlayer insulating film 12 on a silicon semiconductor substrate 11. The upper face part is exposed by removing the second insulating film 14, and a first metallic layer 17 is selectively grain to cover the upper surface and the upper side face thereof. A through hole is formed above the first metallic layer 17, and a second metallic wiring layer 22 is formed after a second metallic layer 21 is formed to fill up the through hole. Consequently, a through hole 20 formed therein is almost equal in width to the first metallic layer 17, but the first metallic layer 17 is larger in width than the first metallic wiring layer 13 so that a space margin for mask alignment can be ensured during a through hole forming step. Moreover, the first metallic wiring layer 13 on a smaller pitch P0 can be formed without damaging the first interlayer insulating film 12 or the first metallic layer 13.