PURPOSE: To detect a clock phase error by using the simple arithmetic circuits for the delay, addition, subtraction, inversion, etc., in place of the complicated differential and squaring circuits, etc.

CONSTITUTION: A delay circuit 2 outputs a 1st delay signal (b) obtained by delaying the input signal (a) of a signal I or Q obtained from the synchronization detection by the 1-clock time. A delay circuit 6 outputs a 2nd delay signal (c) obtained by delaying the signal (b) by a single clock. An average circuit 10 outputs an addition average signal (d) by adding and averaging the signals (a) and (c). A subtractor circuit 8 outputs a 1st difference signal (e) obtained by subtracting the signal (d) from the signal (b). A subtractor circuit 4 outputs a 2nd difference signal (f) obtained by subtracting the signal (a) from the signal (c). An inverting circuit 11 outputs the signal (e) as it is as a clock phase error signal when the code of the signal (f) is positive and then outputs the signal (e) after inverting it as a clock phase error signal when the code of the signal (f) is negative respectively.