Title:
【発明の名称】半導体メモリ装置
Document Type and Number:
Japanese Patent JP3084801
Kind Code:
B2
Abstract:
The semiconductor memory device according to this invention is constituted by including a memory cell array which consists of a plurality of memory cells that are arranged in array form in row and column directions and a plurality of bit line pairs that respectively connect these memory cells in common for every column and word lines that respectively connect these memory cells in common for every row, a sense amplifier connected to each member of the bit line pair at one end of said bit line pair for amplifying the potential difference between the pair of bit lines, a transfer gate provided between one end of the bit line and the sense amplifier; and a potential supply circuit connected respectively to the bit line pairs between the sense amplifiers and the transfer gates and supplies a signal having a potential level that corresponds to a simultaneous write data to one member of the bit line pair when the transfer gate is closed earlier than the time at which a predetermined one of the word lines is selected. By the adoption of the above-mentioned constitution the simultaneous writing becomes possible by a circuit modification which hardly affects the chip size.
Inventors:
Yasuharu Hoshino
Application Number:
JP18310491A
Publication Date:
September 04, 2000
Filing Date:
June 27, 1991
Export Citation:
Assignee:
NEC
International Classes:
G11C11/409; G11C7/00; G11C11/401; (IPC1-7): G11C11/401
Domestic Patent References:
| JP599960A | ||||
| JP59132493A | ||||
| JP1286195A |
Attorney, Agent or Firm:
Seiichi Kuwai